This invention relates generally to level shifting circuitry and more particularly to the problems of level shifting in high-speed operational amplifiers and other feedback amplifiers, particularly as incorporated into analog integrated circuits.
Level shifting is a general requirement in feedback amplifiers with large common mode input ranges and large output voltage swings. FIG. 1 illustrates, in block diagram form, a typical operational amplifier or feedback amplifier. A desired differential signal V.sub.id and a common mode signal V.sub.icm are applied to an input stage. The input stage is conventionally biased relative to a supply voltage or other reference voltage V.sub.ref2 by appropriate bias circuitry, such as a current source. The potential V across the input stage must be maintained so as to meet the minimum voltage requirements for the input stage to operate.
The differential outputs of the input stage are connected to load circuits and input to a second stage, such as a level shifter. The load circuits are biased at a potential relative to another supply voltage or other voltage reference, V.sub.ref1. The potential across the load circuits, V.sub.1, is determined by the designer to meet the requirements for proper operation of the load circuits and the second stage. The level shifter has an output which must be at a sufficient potential, V.sub.2, relative to voltage reference V.sub.ref2 to interface to a third stage circuit (not shown). Thus, the level shifter should provide or absorb a voltage drop so as to produce the desired input potential V.sub.1 given the output potential V.sub.2. If both polarity-type devices are available in a given technology, a level shifter can be implemented as a common-emitter (source) stage, or as a common base (gate) stage of a polarity type opposite that of the input stage. In this case, the collector-emitter (drain-source) absorbs the difference in potential between the input and output of the level shifter. In a single polarity technology, or in a technology where only one polarity device is of high bandwidth, an alternative means is necessary to drop the required voltage.
These factors present difficult constraints within which the designer must design the level shifter. In addition, it is desirable for the common mode range to be as close as possible to the power supply voltages. Also, the supply voltages are subject to variations, for example, by design or due to temperature variations. Accordingly, designers conventionally choose a potential V.sub.1 that is large enough to compensate for the expected range of such variations. Doing so, however, reduces common mode range and may require trade-offs with respect to output voltage swing.
Single polarity prior art circuits result in non-optimum values of potential V.sub.1 that do not adapt to power supply, process and temperature variations in a desirable way. Also, prior art implementations of level shifters typically incorporate components and combinations of components that are non-optimal, particlarly for high-speed performance. One such implementation includes the use of lateral PNP transistors, which are too slow for wideband applications. An alternative implementation could use avertical PNP transistors if the fabrication process being used allows for it. This fabrication process is expensive, requiring extra processing and probably resulting in lower yields than less complex technologies. Vertical PNP transistors, in any event, are generally of lower bandwidth than NPN transisters. In many fabrication technologies, vertical PNP transistors or p-channel FETs are not available at all. Some prior art level shifters employ Zener diodes but these are noisy, unsuitable for a wide range of power supply voltages, and have a limited common mode range.
Accordingly, a need remains for a level shifter design that is capable of high-speed operation (at frequencies in excess of 1 GHz), is capable of adjusting in operation to supply, process (i.e., transistor parameters) and temperature variations, is capable of being implemented with a single polarity device, and frees the circuit designer from such tight design constraints.